Patent us3959816 method and apparatus for interpreting binary data
This application is related to application Ser. Chi; to application Ser. Whitfield; and to application Ser. The entire disclosures of each of these applications are incorporated by reference herein.
Each of these applications is copending and commonly assigned. This invention relates to electrical circuits suitable for decoding binary information, in accordance with either of two novel modulation methods. Novel methods for modulating binary data or information into a format suitable for encoding and decoding e. Wash, andto C.
The novel methods both feature self-clocking, velocity insensitive encoding and decoding. Electrical circuits that may be employed for realizing the decoding schemes set forth in the Wash method are disclosed in the above-cited application Ser. The electrical circuits of the present application, in contrast, have an advantage that they may be employed for decoding information that has been encoded in accordance with either the Wash or Chi methodologies. The novel, multi-purpose electrical circuits of the present invention decode the information, and preserve the self-clocking, velocity insensitive features of the novel methods.
The novel methods of Wash and Chi are first set forth, with examples, in order to provide a perspective for the present invention. Accordingly, in one embodiment, Wash discloses a method for modulating binary data comprising first and second information, the method comprising:.
An example of the Wash method is shown in FIG. Note that some of the Wash lexicography has been re-phrased in FIG. For example, a "bitcell" is now referenced as an "information-cell". Each of the information-cells is demarcated by a pair of negative clock transitions. A first information, a data 0, is encoded in the first information-cell, while a second information, a data 1, is encoded in the second information-cell.
Note that the encoding of the information transitions for both the first and second information-cells leaves invariant the negative clock transitions. We now set forth the Chi method, and an example. In one aspect, Chi discloses a method for modulating binary data comprising first and second information, the method comprising:. An example of the Chi method is shown in FIG. Note that some of the Chi lexicography has FIG.
Note that some of the Chi lexicography has been re-phrased in FIG. For example, an "event-cell" is now referenced as an "information-cell". Thus, by definition of the Chi method, the first information-cell encodes the data 0, since it comprises generating a first event at an arbitrary time, by generating three alternate information transitions; the first event realizing, downstream, a first read signal. Again, by definition, the second information-cell encodes the data 1, since it comprises generating a second event, at an arbitrary time, by generating a single information transition; the second event realizing, down-stream, a second read signal.
With the intent of providing a means for decoding an encoded signal, encoded either by way of the Wash or Chi methods, as exemplified in FIGS. The present invention, as defined, has an advantage that it may be employed to decode a signal encoded either by way of the Wash or Chi methods, cited above.
This versatility applies not only to the two illustrative encoded signals shown in FIGS. For example, the present invention can decode the more generalized, complex encoded signals shown in FIGS.
The point is that the Wash and Chi methods can give rise to an indefinite number of alternative encoded signals, all within their generic formats respectively, and all capable of being readily decoded by the present invention. The present invention, as defined, has a further advantage of preserving the self-clocking, velocity insensitive features of the Wash and Chi methods.
This preservation factor is provided by the electrical circuit in the following way. First, it is evident from the illustrative FIGS. The present electrical circuit accommodates such unpredictable and variable transfer rates by way of a two-fold capability. First, the electrical circuit identifies or re-creates, on the decoding end, the encoded, variable sequential information-cells. This is accomplished, inter alia, by way of the operation of the counting means and the computing means.
Second, the electrical circuit, having identified the succession of variable information-cells, signifies each identified information-cell as being dedicated to either a first or second information.
The signification is based on a known relationship between the first and second formulas. For example, for the Wash encoded signal, the signification turns on knowing where the line of demarcation that uniquely sets off the first and second informations, has been invariantly located within a variable information-cell.
To this end, the first formula can effect a counting regime that is a measure of the invariant line of demarcation; and the first formula, in ratio to a combined count of the first and second formulas, can re-create the line of demarcation with respect to the entire and variable information-cell, thus signifying the instant information-cell as being either a first or second information.
For the Chi encoded signal, on the other hand, a simple quantitative comparison between the yield of the first and second formulas, can provide the signification of a first or second information in a variable information-cell.
The present invention has a further advantage of having a bi-directional decoding capability, as well as a uni-directional decoding capability. Further, the decoding may be accomplished in "real-time", i. Thus, the present electrical circuits do not "look-back", in analeptic fashion, to re-create an information-cell, but rather provide a proleptic or real-time capability, for determining the signification of the information-cell.
This is true because of a direct counting capability inherent in the first and second formulas. Attention is now directed to FIG. The structure of the circuit 10 is first disclosed, followed by its operation. The head 12 reads an encoded signal, as explained more fully below, and outputs a read signal along a line pair The read signal is amplified by a pre-amplifier 16, filtered by a filter circuit 18, again amplified by a post-amplifier 20, and inputted along a line 22 to a detector means Appropriate line pairs for processing the read signal are provided by line pairs 26, The detector means 24, in turn, comprises a positive threshold peak detector 30, and a negative threshold peak detector 32 connected in parallel to the positive threshold peak detector The positive threshold peak detector 30 outputs an information pulse train signal, along a line 34, for input to a clear terminal of a flip-flop 36; while the negative peak detector 32 outputs a clock pulse train signal, along a line 38, for input to a time delay 40, and for input to a computer 42, along a line The time delay 40, in turn, provides an input, along a line 46, to a set terminal of the flip-flop 36, as well as an input, along a line 48, to a clear terminal of a counter The counter 50 provides counting outputs from a least significant bit LSB to a most significant bit MSBalong lines 58, 60, 62, 64 respectively, the last also inputted to the computer The operation of the FIG.
An objective of the operation of the circuit 10 is to first decode binary data comprising first and second informations, which data has been encoded into an encoded signal shown in FIG. Negative clock transitions set-off the two information-cells. The head 12 reads the FIG.
Continuing, the read signal comprising clock transition components, and first and second information components, as exemplified by FIG.
For pedagogical purposes, it is assumed that the input waveform to the detector means 24, after the electronics, is substantially equivalent to that already shown in FIG. The detector means 24, by way of the positive and negative threshold peak detectors 30, 32 respectively, interrogates the FIG. In particular, the output of the negative threshold peak detector 32, shown in FIG.
The separate first and second pulse trains input to a set of logic devices, namely, the flip-flop 36, the counter 50 and the computer Taken conceptually as a whole, the operation of the logic devices follows a four-step procedure see the timing diagrams FIG.
Preferably, the counter 50 counts according to a first formula given by the FIG. This action, in turn, again by way of line 52, now initiates the counter 50 to count according to a preferred second formula given by the FIG. The most significant bit MSB of the last count is inputted along the line 64 to the computer 42.
The computer 42 may be programmed see illustrative program set forth below to signify whether the identified first information-cell is dedicated to a first or second information. Here, the signification is direct: This is true for the following reason. In the further count down, until the information-cell elapses, the 1 in the MSB must always continue to appear, i.
But this fact, by definition of the Wash encoding method, means that the information 0 is encoded in the first information-cell. The second information-cell subsumed in the FIG. This is clear from the FIG. In other words, the MSB must remain a zero.
But this fact, by definition of the Wash encoding method, means that the information 1 is encoded in the second information-cell. Additional instruction on the operation of the circuit 10, as it relates to the Wash method, is now disclosed.
First, the clock transitions in the FIG. In other encoding signals, not shown, these transition polarities may be respectively reversed, while still uniquely distinguishing the clock from information transitions. The electrical circuit 10 may be readily adapted to decode this alternative encoding signal.
Second, as indicated in the Summary above, the information transitions and line of demarcation of an encoded signal can be located at any predetermined information-cell location, with any change being readily accommodated by the circuit Third, the circuit 10 preferably employs the time delay 40, interposed between the detector means 24 and the flip-flop 36, to shift the clock transition pulse train by a predetermined time, as shown in FIG. This action obviates a potential ambiguity that clock pulses could occur simultaneously, hence ambiguously, with information pulses.
Other techniques, among many, to avoid the indicated potential ambiguity, include using a leading and a trailing edge of the clock pulse to set the flip-flop 36, and input to the computer Fourth, the circuit 10 preferably employs a systems clock 56, inputting into the counter 50 along the line 54, for coordinating overall timing operations of the circuit The systems clock 56 timing profile for the above embodiment is shown in FIG.
Fifth, while the counter 50 preferably employs the above disclosed first and second counting formulas, namely counting up and down by one, from a zero  origin, it is possible to employ many other, alternative counting formulas. For example, the counter 50 can first count down by two's, from an arbitrary origin [wxyz], then count up by ones, at the advent of the information pulse. In these cases, of course, the MSB outputted by the counter 50 to the computer 42 may not immediately be the signification of a first or second information, and this must be factored, accordingly, into the computer 42 program.
However, alternative embodiments simulate the counter 50 capabilities by way of an appropriately programmed computer Seventh, the circuit 10 makes use of, e. Conventional such components can be used for this purpose including, for example, a Texas Instruments Model No.
We now turn our attention to the operation of the FIG. A representative Chi encoded signal has been discussed above see FIG. The processing of the Chi encoded signal is entirely analogous to that of the Wash encoded signal, with the following noted exceptions. First, the read signal is of the form shown in FIG.
The present invention relates to improvements in a tape transport system and in a method for decoding digital data stored on audio, tape by an audio tape recorder.
This discloure hereby incorporates by reference the entire disclosure of the patent application of Ellis K. Cave, one of the co-inventors hereof, entitled "Automated Conversation System," having serial no. One of the features of the "Automated Conversation System" is a processor, controlled system having two tape recorders, one of the tape recorders having prerecorded on one of its tracks a set of vocalizations on the particular subject about which the conversation system is to converse, and on a parallel track having prerecorded thereon digital data corresponding to the vocalizations.
The Automated Conversation System accesses various vocalizations using the digital track for guidance. After a vocalization or even during the vocalizationthe second tape recorder records all information from the person carrying on the conversation. Such information may be in the form of vocalizations or can be data transmitted via a telephone line in the same manner by which a telephone is placed, i.
The present invention in one of its aspects relates to a method and apparatus by which the digital data stored on the track of the first tape recorder is decoded for use by a microprocessor.
Another aspect of the invention relates to achieving a two-way conversation without undue gaps on behalf of the system. Unless the tape recorder can move both quickly and accurately to such a select position, part of the vocalization will be lost or time will be wasted patent us3959816 method and apparatus for interpreting binary data the tape recorder zeros in on the selected tape position.
It is therefore an object of the present invention to provide an improved method and apparatus by which a tape can moved to a selected position. It is another object to provide a method and apparatus for moving a tape to a selected tape position in a relatively low-cost audio tape recorder. Another object of the present invention is to provide an improved braking system for a tape transport. Still a further object of the present invention is to provide a braking system for the tape transport in a relatively low-cost audio tape recorder.
In describing various aspects of the present invention, reference is made the accompanying patent us3959816 method and apparatus for interpreting binary data, wherein:.
Figure 1A is a sketch representing a view of means on a portion of a tape transport for generating signals as the tape transport moves. Figure IB is a sketch representing a side view of the means of Figure 1 as well as other representative, portions of a tape deck; and.
Figure 2 is a. According to one aspect of the invention, a magnetic recording tape may be prerecorded with digital data on one of two or more parallel tracks. Each digital datum identifies its own position on the tape. On the other track, audio vocalizations may be prerecorded. Such prerecording can be done on a tape recorder equipped with means on a tape transport for generating signals based on movement of the transport.
For example, referring to Figure 1A and IB, a tape recorder having a motor 10 with a axle 12 can rotate a flywheel 14 via a. The flywheel may include an aperture 20 through which light passes along an optical path 22 from a light source 24 to a photocell Each time aperture 20 passes through the patent us3959816 method and apparatus for interpreting binary data path, the electrical signal outputted by photocell 26 changes. Such electrical signals will represent the position of the tape in the tape transport.
Accordingly, during the prerecording stage, a catalog can be made to associate the number of counts of changes in the electrical signal outputted by photocell 26 patent us3959816 method and apparatus for interpreting binary data the various vocalizations on one track of the magnetic recording tape.
Advantagiously, the digital data is also correlated to the vocalizations. When the tape is placed in a tape deck. Signals from photocell 26 can increment the count in a storage device such as a memory 28 directly via lines 29 or via control means such as a microprocessor 30 via leads When the tape moves in a "read" or playback position, a playback head 32 will read the audio vocalizations on one track and the digital signals on the other track.
The digital signals will be applied to processor 30 which communicates with memory 28 via a lead or bus Processor patent us3959816 method and apparatus for interpreting binary data updates memory 28 to correctly reflect the actual position tape which will be read directly from the tape without any error tape slippage or the like which could cause a miscorre- lation of the position of the tape transport mechanism with the actual position of the tape.
A command may be given to move the tape to a particular location. Such a command can be inputted on an input lead 36 from a command authority such as a system user or a central processing unit at a remote, location. Alternatively, the command to go to a particular tape location can be generated by processor 30 of its own accord, depending on system organization. The motor may illustratively be put into a rewind position. Normally the playback head 32 is not engaged with the tape during a rewind operation, so the movement of the tape is monitored by pulses generated by photocell It is to be understood that the updating can occur at various times and with various frequency, although highly accurate results will be obtained when the updating is done after each digital indication of tape position is read.
Another aspect of the present invention relates to the braking of the tape transport when going to a. Referring again to Figure 2, when a command is generated or inputted to move the tape to a selected position, processor 30 activates motor 10 to move the tape toward the selected position.
Processor 30 patent us3959816 method and apparatus for interpreting binary data the count of memory 28 and when the count, approaches the selected position count, processor 30 activates a brake Sometime after the braking application, processor 30 determines the position of the tape by reading memory 28 or by itself monitoring the number of counts generated by photocell Processor 30 then determines whether the tape is at the.
Processor 30 then causes motor 10 to move the tape toward the selected tape position and at the subsequent, tape position again engaging brake After the tape stops, the processor determines whether the tape is at the selected tape position. If it is not, the processor 30 reiterates the tape position adjustment by determining the new difference in position, calculating a new subsequent tape position, restarting motor 10 and rebraking at the new subsequent position.
It will be appreciated that the methods and apparatus described herein will facilitate the use of relatively inexpensive tape transports such as may be found in low-cost audio tape recorders or decks for highly accurate and quick tape positioning, such as may be required in telephone banking or other applications where a machine must communicate with a person. Other applications of the present invention will be apparent. Moreover, it will be clear to those who are skilled in the art that various modifications patent us3959816 method and apparatus for interpreting binary data alterations can be made to the preferred embodiment hereof.
It is therefore intended that the scope of protection afforded be determined by the appended claims. Improved magnetic tape transport arrangement allows rapid and accurate access to selected tape positions. The tape includes at least one track containing a recording of an index.
The transport has associated with it a means for indicating tape transport movement, illustratively an aperture 20 in the tape patent us3959816 method and apparatus for interpreting binary data 14 for permitting passage of light 22, 24 to a photosensor 26 from time to time in accordance with flywheel movement. A processor 30 and associated memory 28 are connected 31, 29 to the optical system so that the memory 28 registers the apparent position of the tape based on the number of times the light beam 22 passes through the aperture From time to time as the tape is played the tape head 32 reads digital data and this is inputted to the processor 30 which corrects the memory 28 count, if necessary, of the tape position.
To move the tape to a desired location, the intended position is applied by appropriate means 36 to the processor. The processor 30 calculates the number of increments needed to patent us3959816 method and apparatus for interpreting binary data the intended position based on the data in memory 28 and commands a motor 10 and brake 38 system to move the tape in that direction.
The processor monitors the memory count which changes each time the aperture 20 permits the light beam 22 to pass, and causes brake 38 application prior to reaching the intended position. The processor thereafter continues monitoring the memory 28 and controlling the motor 10 and brake 38 until the desired tape location is reached.
With the disclosed system, inexpensive tape transport can be used for accurate and quick tape positioning. Figure 1A is a sketch representing a view of means on a portion of a tape transport for generating signals as the tape transport moves; Figure IB is a sketch representing a side view of the means of Figure 1 as well as other representative, portions of a tape deck; and Figure 2 is a.
A method for decoding modulated digital data recorded by an audio recorder on audio tape comprising: The method of claim 1 further comprising the step of first filtering the corresponding signals to remove noise therefrom. Apparatus for decoding modulated digital date stored on audio tape by an audio tape recorder comprising: The apparatus of claim 3 further comprising a hysteresis comparator receiving playback signals from said tape redcorder and having its output coupled to said transition detector.
The method of cl aim 5 further comprising storing a catalog associating projected sensed position signals with said set of marker signals. The method of claim 7 wherein said storing comprises prerecording said catalog on said tape, reading said catalog, and storing said catalog in a memory position. The method of claim 7 wherein said moving step comprises determining the number and direction by which said count in said storage device must be incremented to reach the marker signal for the selected position as indicated by said catalog.
The method of claim 5 or 9 wherein said determining step and said adjusting step precede said moving step. The method of claim 5 or 9 wherein said determining step and said adjusting step patent us3959816 method and apparatus for interpreting binary data said moving step.
A system for accurately moving recording tape to a selected position comprising: I in terms of a marker signal correlated to the selected position to which said tape is to be moved. A machine implemented method for braking a tape transport when moving tape from an initial tape position to a selected tape position so that the tape stops at the selected position comprising: The m ethod of claim 14 wherein step a includes moving an apertured device associated with the tape transport to intercept and then clear an optical.: The method of claim 16 wherein said first tape position corresponds to a count in said storage device which differs from a count corresponding to the selected tape position by patent us3959816 method and apparatus for interpreting binary data predetermined number of counts.
The method of claim 14 wherein each of said subsequent tape positions has a predetermined relationship to the selected tape position and the relavant determined tape position.
The method of claim 14 wherein said. A system for accurately braking a tape moving from an initial tape position to a selected tape position in a tape transport comprising: Additional device for a videorecorder allowing access to parts of a tape with a precision of the order of seconds.
Disk reproduction apparatus and method for high speed accessing of desired information data by checking address data. Apparatus for recording and reproducing data on and from a storage device having a plurality of kinds of storage media integrally provided therein. Calibrating optical disk recorders to some parameters during disk spin up while deferring calibration of other parameters. Information reproduction apparatus having means to control maximum delay of information being read from memory.
Recording method, recording apparatus, reproducing method and reproducing apparatus. Method and apparatus for scanning and recovering information from a record medium. Disc player having pick-up tilt servo system combined with disc presence detection circuits. Apparatus for rewriting an optical disc while updating its table of contents and without leaving gaps.
Head exchange system for disc drive system controlling busy signals in accordance with head offset.
The present invention relates patent us3959816 method and apparatus for interpreting binary data a method and apparatus for patent us3959816 method and apparatus for interpreting binary data digital data for transmission or recording and also a method and apparatus for decoding the encoded signal produced by the encoder apparatus. There are a number of methods and devices for encoding electrical signals for transmission over a long cable or for recording on a medium such as magnetic discs or tapes.
Some of the more commonly known types of digital data encoding methods include the method of frequency-encoding digital signals such as described in U.
In these systems, a predetermined frequency signal represents the digital "1" and a different predetermined frequency signal represents digital "0". Through circuitry at the receiver, these various frequencies are separated from patent us3959816 method and apparatus for interpreting binary data transmitted signal and a digital signal is reconstructed. The receiver, however, must be synchronized with the transmitter so that the data information can be determined.
One way of doing this is to provide a separate synchronizing clock signal in addition to the data patent us3959816 method and apparatus for interpreting binary data being transmitted.
The receiver recognizes this clock signal and clocks the receiving circuit to receive the incoming data. Another method involves what is called phase encoding patent us3959816 method and apparatus for interpreting binary data data. This method of encoding is described, for example, in U.
For example, an output signal transition in one direction from high voltage to low voltage is used to represent a binary "0", and a transition in the other direction, low voltage to high voltage, is used to represent a binary "1". An advantage of phase encoding digital type systems is that it is "self clocking". More specifically, it is not necessary for the transmitted signal to include a separate clock signal to synchronize the receiver with the transmitter.
In a phase encoding method, the data transitions occur with sufficient regularity that a clock signal can be derived from the data being transmitted in a well known manner by using averaging methods.
The present invention is an improvement over known data encoding equipment and methods. The transmittal signal according to the present invention is a string of truncated and extended pulses, the truncated pulses correspond to a digital "0" and the extended pulses correspond to a digital "1". Further, the frequency of the leading edges of all the pulses is the clock frequency such that a clock signal can be generated by the receiver directly to synchronize the receiver to the transmitter.
With the present invention, the leading edge of each pulse encoded by this technique contains the information regarding the frequency of the clock signal, and the trailing edge of the transmitted pulse contains the data information. Specifically, the pulse is varied in length with a truncated pulse corresponding to a digital "0" and an elongated pulse corresponding to a digital "1".
With the present invention, data can be transmitted at the clock rate and a separate clock signal is not necessary. Further, many of the problems known in the prior art such as "bit shifting" described in U.
Many of the problems with phase encoding of data, for example, occurred because there was no signal transmitted for a binary "0", thus the clock signal had to be derived from the overall string of pulses. With phase encoding apparatus, complicated averaging circuits and other types of circuits are provided to indirectly derive a clock signal so that the receiver can be synchronized with the transmitter.
All of these other circuits can be eliminated with the present invention. In order that the invention may be clearly understood and readily carried into effect, a preferred embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings wherein:. A digital data encoder 21 is shown schematically in FIG. This encoder includes a conventional shift register 22 such as Model 74HC manufactured by the National Semiconductor Company.
This shift register 22 is described in the " CMOS Databook" distributed by National Semiconductor Company and this manual is hereby incorporated by reference. The shift register 22 has terminals numbered 1 through 20 as shown in FIG. The terminals 2, 3, 10 and 11 of shift register 22 are connected to ground. A clock pulse from a conventional clock signal source not shown is applied to terminal 12 of the shift register In the embodiment shown in FIG.
Each bit of the digital signal is applied to the shift register 21 through the leads D0-D7 as indicated in FIG. These leads are connected to the shift register 22 as follows: D0 to terminal 7 of shift register 22; D1 to terminal 13; D2 to patent us3959816 method and apparatus for interpreting binary data 6; D3 to terminal 14; D4 to terminal 5; D5 to terminal 15; D6 to terminal 4; and Patent us3959816 method and apparatus for interpreting binary data to terminal A time slot lead 24 transmits information concerning the byte size of the digital signal to be transmitted to terminal 19 of the shift register This time slot information is produced by a source not shown and depends upon the byte size to be transmitted.
The shift register 22 is used to prepare the data to be transmitted for encoding. Essentially, the data to be transmitted is clocked into the shift register 22 through the leads D0-D7 and the information as to the byte size of the information to be transmitted is also transmitted to the shift register through lead Once the data has been clocked into the shift register, the data is then ready for encoding.
In order to accomplish the encoding, a conventional dual one shot 26, such as Model 74HC manufactured by the National Semiconductor Company is used. This dual one shot 26 is described in the " CMOS Databook", which manual is also incorporated herein by reference.
This dual one shot 26 has sixteen terminals numbered 1 through 16 as shown in FIG. Terminals 4 and 12 of this dual one shot 26 are not used. Terminals 1, 8 and 9 of dual one shot 26 are grounded. The clock pulse transmitted to the shift register 22 is connected to terminals 2 and 10 of the dual one shot When the data is to be encoded, the data which is located in shift register 22 is transmitted via line 30 connected to terminal 17 of the shift register 22 to an AND gate 32 and also to an AND gate 34 through an invertor 36 as shown in FIG.
The data to be transmitted is going to be converted with these two AND gates from a pulse corresponding to a digital "1" to a positive pulse having an extended length from a digital "0" which is represented by the absence of a pulse to a positive pulse of a truncated length, as will be described.
The extended pulses representing the digital "1" are created by the dual one shot The length and time of these pulses is determined by a conventional RC circuit consisting of a resistor 38 and a capacitor The resistor 38 is connected to the positive source VCC and has its other end electrically connected to terminal 7 of the dual one shot 26 and to terminal 6 of dual one shot 26 through the capacitor The truncated pulses representing the digital "0" are created by another RC circuit comprising a resistor 42 and a capacitor The resistor 42 is connected directly to the positive source VCC and to the terminal 15 of dual one shot This resistor 42 is also electrically connected in parallel to terminal 14 of dual one shot 26 through the capacitor With this arrangement, a series of truncated pulses is created by the dual one shot 26 at terminal 13 of dual one shot 26 and as shown in waveform B of FIG.
The extended pulses appear at terminal 5 of dual one shot 26 as a series of pulses and as shown in waveform C of FIG. The truncated pulses from terminal 13 of dual one shot 26 are transmitted to the second terminal of AND gate 34 as shown in FIG. The extended pulses appearing at terminal 5 of the dual one shot patent us3959816 method and apparatus for interpreting binary data are directed to the second terminal of the AND gate 32, as also shown in FIG.
The output of AND gates 32 and 34 are directed to an OR gate 45 and the output of the OR gate 45 is either a truncated pulse or an extended pulse, depending on whether the bit to be transmitted is a binary "0" or a binary "1" respectively. In operation, the digital byte to be transmitted is clocked into the shift register 22 as previously described.
Once in the shift register, the bits of the digital byte is transmitted from terminal 17 to the AND gates 32 and 34 also as previously described. If the bit being transmitted is a digital "1", the AND gate 32 will permit an extended pulse to be transmitted through the OR gate 45 for the reason that both terminals to the AND gate are at the higher voltage level corresponding with the logic digital signal "1".
On the other hand, the AND gate 34 has a "1" at the terminal for the truncated pulses but has a "0" from the invertor 36 at the other terminal. Therefore the AND gate 34 will not transmit a truncated pulse.
Considering the reverse situation, that is, the data to be transmitted from terminal 17 of the shift register 22 is a digital "0", it can be seen that the AND gate 32 will not transmit an extended pulse but the AND gate 34 will transmit a truncated pulse. With reference to FIG. Waveform B shows the truncated pulses which are created by the dual one shot 26 at terminal 13 thereof. The dual one shot is configured to produce a truncated pulse each time the patent us3959816 method and apparatus for interpreting binary data pulse is in transition from a low voltage to a high voltage.
Similarly, the dual one shot 26 produces a series of extended pulses at terminal 5 thereof, the extended pulses having leading edges which correspond to the transition of the clock pulse from the low voltage to the high voltage as shown in waveform C of FIG.
Waveform E shown in FIG. This data is one byte which consists of eight bits, and for this example, is the byte "" corresponding to the decimal number "55".
The time slot information is shown in waveform H of FIG. Once the data from the shift register shown in waveform E of FIG. This signal to be transmitted has a truncated signal corresponding to the digital "0", and the leading edge of this truncated pulse corresponds to the transition of patent us3959816 method and apparatus for interpreting binary data clock pulse from a low voltage to a high voltage.
The digital "1" to be transmitted consists of an extended pulse which also has a leading edge which corresponds to the transition of the clock waveform from the low voltage to the high voltage. Thus the patent us3959816 method and apparatus for interpreting binary data edge of each of the pulses whether truncated or extended correspond to the transition from the low voltage to the high voltage in each cycle of the clock. Thus the clock information is contained in the leading edge of the transmitted signal.
Further, the length of the pulse is determinative of the information being transmitted such that an extended pulse is digital "1" and a truncated pulse is a digital "0". Thus the trailing edge of the transmitted signal includes the information with respect to whether a digital "0" or a digital "1" is being transmitted.
The digital decoder 46 is shown in FIG. The schematic circuit is similar to the encoder circuit of FIG. The encoded data transmitted from the encoder 20 is applied via lead 52 to an AND gate 54 and, at the same time, to terminal 10 of dual one shot Leading edges of the transmitted signal as shown in waveform F of FIG.
Therefore the dual one shot 48 recreates the clock signal which appears at terminal 5 of the dual one shot Further, an inverted clock signal appears at terminal 12 of the dual one shot 48 patent us3959816 method and apparatus for interpreting binary data is transmitted to the second terminal of the AND gate 54 such that when the inverted clock waveform goes positive and the waveform of the transmitted signal patent us3959816 method and apparatus for interpreting binary data positive, a pulse appears at the output of the AND gate Note that a pulse is provided only for the extended pulses, that is for the digital "1" of the transmitted signal.
This is because only the portion of the extended pulse beyond the length of the clock pulse will be permitted to be transmitted through AND gate There is no pulse formed for the digital "0" portion of the transmitted signal. The output of the AND gate 54 is applied to terminal 2 of the dual one shot Terminals 1, 8 and 9 of the dual one shot 48 are connected to ground, as shown in FIG. The dual one shot 48, upon receipt of the signal from AND gate 54, recreates a data signal in which the binary signal includes pulses having approximately the same length as the original data signal corresponding to the digital "1" and wherein the binary "0" is represented by the absence of a pulse.
This is accomplished with the RC circuits provided with resistor 56 and capacitor 58 and also resistor 60 and capacitor The recreated data signal is shown as waveform G in FIG. This data is clocked through lead 64 under the clock control appearing on lead 66 which is applied to terminal 12 of shift register 50 into the shift register 50 at terminal Terminals 2, 3 and 10, are connected to ground, and the time slot window recreated by shift register 50 appears on lead 68 connected to terminal 19 of shift register The eight bits of data in the digital byte appear as follows: D0 at terminal 7, D1 at terminal 13, D2 at terminal 6, D3 at terminal 14, D4 at terminal 5, D5 at terminal 15, D6 at terminal 4 and D7 at terminal Thus it is possible to reconstruct the digital signal which was encoded by the encoding apparatus 21 as shown in Patent us3959816 method and apparatus for interpreting binary data.
With the present invention, it is patent us3959816 method and apparatus for interpreting binary data to transmit data which has been encoded with the encoder 21 at clock speeds, with the clock information being carried by each pulse of the pulse train being transmitted.